Semiconductor integrated circuits (IC) are typically formed by performing a sequence of fabrication steps applied to a silicon wafer. For example, the fabrication steps may include photolithography, etching, film deposition, and so on. Processing conditions at various steps may negatively or positively affect the final IC device's performance. The negative effects could be a smaller process window, a lower image contrast, a smaller Depth Of Focus (DOF), and a higher Mask Error Enhancement Factor (MEEF). In contrast, the positive effects could be a larger process window, a higher image contrast, a larger DoF, and a lower MEEF. Furthermore, processing conditions at one step may affect or be affected by another fabrication step. Finding a combination of processing conditions for multiple steps that yields an optimal result on the final IC can be a challenging task.
Traditionally, such a finding has been made by trial and error. Recently, computer simulation tools have been developed to reduce the guesswork in the above process. However, existing approaches are not completely satisfactory. For example, typically only one process condition is input to the simulation tool, which makes the process of tuning multiple parameters a time-consuming task. Further, such approach may overlook dependencies among process parameters, and may fail to find the optimal combination of process conditions. Still further, how to build a simulation model that closely matches a real IC device is also a challenging task. Improvements in these areas are desired.